SUBJECT NAME: VLSI DESIGN. SUBJECT CODE: EC UNIT I CMOS TECHNOLOGY. PART –A (2 MARKS). 1. What are four generations of Integration. EC / EC64 VLSI Design 2 Marks With Answers ECE 6th Semester Regulation | BE Electronics and Communication Engineering. Sixth Semester. 2 MARK QUESTION AND ANSWERS. ECVLSI DESIGN is CMOS technology? Complementary Metal Oxide Semiconductor (CMOS)in which.
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What are the various ways to reduce the delay time of a CMOS inverter? These primitives are instantiated like modules except that they are predefined in verilog and do not need a module definition.
What are the features of standard celled ASICs? Event-based timing control 3. Give marke basic inverter circuit.
Give the different bitwise operators. Short-Circuit and Open-Circuit Faults The effective length of the conductive channel is actually wlth by the applied voltage VDS, increasing VDS causes the depletion region at the drain junction to grow, reducing the length of the effective channel. What is known as test data register? Why is the propagation delay in a carry select Adder is linearly proportional to N?
Hold time is always measured from the rising clock edge to a point after the clock edge. Why was PAL developed? This is used in circuits where it is impossible to fault every node in the circuit. What are the different levels of design abstraction at physical design. In this circuit realization the PMOS network is identical to the NMOS network rather than being the conduction complement, so the topology is called a mirror adder.
The test-data registers are used to set the inputs of modules to be tested, and to collect the results of running tests.
Latches are level sensitive and flip flops are markd sensitive. What are the steps performed to achieve lithography friendly design? What are the different methods of programming of PALs? Regular event control 2. The programmable logic plane is programmable read only memory PROM array that allows the signals present on the devices pins to be routed to an output logic macro cell.
All 6th Semester ECE Question Paper and 2 Marks with Answers – Kiruba Edition
No Latch-up Due to absence of bulks transistor structures are denser than bulk silicon. Power is the rate at which energy is delivered or exchanged; power answsrs is the rate at which energy is taken from the source VDD and converted into heat electrical energy is converted into heat energy during operation.
What is glitch power dissipation?
Low delay sensitivity to load. Violate monotonicity during evaluation phase. It must be a single group of characters. What is a multiplier circuit? Design turnaround is a few hours.
Fault model is a model for how faults occur and their impact on circuits. Primitive logic function keyword provide the basics for structural modeling at gate level. A number of circuit topologies exist proving that careful optimization of the circuit topology and the transistor sizes helps to reduce the capacitance on the anwers bit 3.
The threshold voltage of a MOSFET is usually defined as marsk gate voltage where an inversion layer forms the interface between the insulating layer oxide and the substrate body of the transistor. Click here to sign up.
EC – VLSI Design 2Marks with Answer and 16Marks Question
Click here to sign up. It makes sense to take this approach only if there are no suitable existing cell libraries available that can be used for the entire design. That makes latch based design more efficient.
The programming of PALs is done in three main ways: Give the two blocks in behavioral modeling. Channels gate array Channel less gate array Only the interconnect is 1. Transistors with channel length less than 3 5 microns are termed as short channel devices. No latch up 2.